1. Field of the Invention
The present invention relates to an AM/FM radio receiver and local oscillator circuit used therein. Specifically, the present invention relates to an AM/FM radio receiver having a configuration so as to generate local oscillation signals for AM and FM broadcasting by one frequency synthesizer using a phase locked loop (PLL) circuit.
2. Description of the Related Art
The superheterodyne system is mainly used in the present commercially available radio receivers. According to this system, the signal of the desired broadcast wave is received by converting the frequency of the desired broadcast wave into a center frequency of an intermediate bandpass filter without changing the center frequency and band characteristics of the intermediate bandpass filter. Conversion of the frequency is done by mixing a high frequency amplified receiving signal and a local oscillation signal with a frequency corresponding to the tuning direction.
The inaccurate frequency of the local oscillation signal causes a deviation of the converted frequency from the center frequency of the intermediate bandpass filter. Therefore, a local oscillation signal with a high-accurate and less-variable frequency is demanded. The PLL frequency synthesizer (hereinafter referred to simply as “PLL circuit”) which is easily controlled by a microcomputer is recently used to the circuit which generates the local oscillation signal. In general, a crystal oscillator which generates a high-accurate and less-variable frequency is used to a reference frequency generator used in the circuit.
A number of commercially available radio receivers may receive both AM and FM broadcast wave. The technologies comprising one PLL circuit which functions as both a circuit for generating the local oscillation signal for converting the AM broadcast wave and a circuit for generating the local oscillation signals for converting the FM broadcast wave are conventionally provided (see Patent Documents 1 and 2).
Patent Document 1: Japanese Patent Application Laid-open No. H8-149031
Patent Document 2: Japanese Patent Application Laid-open No. 2000-165277
FIG. 1 is a functional block diagram showing an example of partial configuration of a radio receiver comprising one PLL circuit for both AM and FM broadcast. As shown in FIG. 1, this type of radio receivers comprises an antenna for FM 1, high frequency amplifier circuit for FM 2, mixer circuit for FM 3, intermediate frequency amplifier circuit for FM 4, antenna for AM 5, high frequency amplifier circuit for AM 6, mixture circuit for AM 7, intermediate frequency amplifier circuit for AM 8, PLL circuit for both AM and FM 9, and divider for AM 10.
In the high frequency amplifier circuit for FM 2, the specific frequency band of the broadcast wave received with the antenna for FM 1 is selectively amplified. The frequency converter for FM consisting of the mixer circuit for FM 3 and PLL circuit 9 mixes a carrier signal with a frequency of fFMRX outputted from the high frequency amplifier circuit for FM 2 and a local oscillation signal with a frequency of fFMLO outputted from the PLL circuit 9 to convert the frequencies, generating an signal with an intermediate frequency (for example, fFMRX−fFMLO=10.7 MHz) to be outputted. The intermediate frequency signal passed through the mixture circuit for FM 3 is amplified in the intermediate frequency amplifier circuit for FM 4.
In FM broadcasting in Japanese band, the allocated frequency is in the range of 76.1-89.9 MHz and the bandwidth occupied by one channel is 100 KHz. Since the local oscillation frequency fFMLO of each channel required for tuning is lower by 10.7 MHz than the carrier frequency fFMRX of the channel, the PLL circuit 9 outputs the signal with a frequency of fFMLO in 65.4-79.2 MHz as the local oscillation signal for selecting FM broadcast wave.
On the other hand, the high frequency amplifier circuit for AM 6 selectively amplifies the specific frequency band of the broadcasting wave received with the antenna for AM 5 in general. The frequency converter for AM consisting of the mixer circuit for AM 7, PLL circuit 9, and divider 10 mixes a carrier signal with a frequency of fAMRX outputted from the high frequency amplifier circuit for AM 6 and a local oscillation signal with a frequency of fAMLO, which is a frequency outputted from the PLL circuit 9 and divided by N in the divider 10, to convert the frequencies, generating a signal with an intermediate frequency (for example, fAMLO−fAMRX=10.7 MHz) to be outputted. The intermediate frequency signal passed through the mixer circuit for AM 7 is amplified in the intermediate frequency amplifier circuit for AM 8.
In AM broadcasting in Japanese band, the allocated frequency is 531-1620 KHz and the bandwidth occupied by one channel is 9 KHz. Since the local oscillation frequency fAMLO of each channel required for tuning is higher by 10.7 MHz than the carrier frequency fAMRX of the channel, the divider 10 divides the frequency fAMLO of the local oscillation signal of 65.4-79.2 MHz outputted from the PLL circuit 9 by N to output the signal with a frequency fAMLO of 11.231-12.320 MHz in the divided frequency as the local oscillation signal for AM broadcasting selection.
The frequency fAMLO of 11.231-12.320 MHz multiplied by six is 67.386-73.920 MHz which is within the range of 65.4-79.2 MHz for the frequency fFMLO of the local oscillation signal for FM broadcasting selection outputted by the PLL circuit 9. Therefore, the local oscillation signal for FM and AM broadcasting can be obtained from one PLL circuit 9 by using the divider 10 with a divide ratio of 1/6 (N=6).
As mentioned above, the local oscillation signal outputted from the PLL circuit 9 is demanded to have a high degree of accuracy and small frequency variation. Therefore, a crystal oscillator with the high-accurate and less-variable frequency is used in the PLL circuit 9 in many cases. FIG. 2 shows the configuration example of the conventional PLL circuit 9 using the crystal oscillator.
As shown in FIG. 2, the PLL circuit 9 comprises a crystal oscillator 11, reference oscillator (OSC) 12, divider 13, phase comparator 14, low pass filter (LPF) 15, voltage-controlled oscillator (VCO) 16, and programmable counter (PC) 17. The reference oscillator 12 generates the reference oscillation signal with the reference frequency using the crystal oscillator 11. The divider 13, which has two divide ratios for FM and AM and is switchable to either ratio, divides the frequency of the reference oscillation signal to be outputted to the phase comparator 14.
The phase comparator 14 compares phases between the reference oscillation signal from the divider 13 and the outputted signal from the programmable counter 17 and outputs the voltage corresponding to the phase difference to the low pass filter 15. The low pass filter 15 removes the undesired frequency outputted from the phase comparator 14 and generates the direct current control voltage to be supplied to the voltage-controlled oscillator 16. The voltage-controlled oscillator 16 varies the oscillation frequency according to the voltage outputted from the low pass filter 15 and outputs the reference clock controlled to be in synchronization with the reference signal. The programmable counter 17 divides the reference clock by the divide ratio corresponding to the selection frequency and outputs the divided clock signal to the phase comparator 14.
The PLL circuit 9 having such configuration operates as described below. The reference oscillation signal outputted from the reference oscillator 12 is divided in the divider 13, being inputted to the phase comparator 14. The local oscillation signal outputted from the voltage-controlled oscillator 16 is divided with the divide ratio corresponding to the selection frequency in the programmable counter 17, being inputted to the phase comparator 14.
The phase comparator 14 compares the phases between the reference oscillation signal from the divider 13 and the outputted signal from the programmable counter 17 to output the voltage corresponding to the phase difference to the voltage-controlled oscillator 16 via the low pass filter 15. With these operations as mentioned above, the local oscillation signal outputted from the voltage-controlled oscillator 16 to the mixer circuit for FM 3 as well as the divider for AM 10 is controlled to be in synchronization with the reference oscillation signal from the divider 13.
Since the divide ratio in the divider for AM 10 is 1/6 and the bandwidth occupied by each channel in the AM broadcasting is 9 KHz as mentioned above, the frequency fr of the reference oscillation signal outputted from the divider 13 during the AM broadcasting selection needs to be 54 KHz. However, a crystal oscillator which generates a low frequency fx of 75 KHz is generally used as the crystal oscillator 11 in radio receivers because the harmonic component is superimposed on the broadcast band and the reception sensitivity deteriorates if the oscillation frequency fx is high.
Being unable to generate the reference oscillation signal with a frequency of 54 KHz by the divider 13 when the crystal oscillator 11 with a frequency of 75 KHz is employed, the divider 13 practically generates the reference oscillation signal with a frequency fr of 3 KHz which is the greatest common divisor between 75 KHz, the oscillation frequency of the crystal oscillator 11, and 54 KHz, the frequency of the reference oscillation signal required for AM broadcasting.
However, the smaller the frequency fr of the reference oscillation signal, the greater the divide ratio in the programmable counter 17 which results in the following problems:    1. The scale expansion of the circuit because the number of columns in the flip flop circuit constituting the programmable counter 17 must be increased.    2. The extension of a lock-up time in the PLL circuit.    3. The deterioration in S/N ratio.